1. Field of the Invention
The present invention relates to data processing devices, and particularly to improvement for increasing processing speed and ensuring storage capacity required for semiconductor memory in a compatible way.
2. Description of the Background Art.
FIG. 13 is a block diagram showing the structure of a conventional data processing device as a background of the present invention. In this conventional device 151, an operation portion 161 containing a microcomputer (hereinafter referred to as a CPU) is connected to memory portions 162 through a bus line 163. The memory portions 162 include DRAMs (Dynamic RAMs), for example. The device portions 161, 162 are formed of individual semiconductor chips (semiconductor substrates).
In this device 151, the operation portion 161 reads and writes data signals from and into the memory portions 162 in units of N bits. The bus line 163 provides the advantage that the memory space accessed by the operation portion 161 can freely be extended by connecting a plurality of memory portions 162.
With the device 151, however, such delays as cannot be neglected occur in transmission of data signals because the data signals are read and written through the interconnection 163 provided outside the semiconductor chips. Further, the number of bits, N, which can be written and read in parallel is limited because one semiconductor chip can be equipped with only a limited number of pins (terminals).
The delays in data signals and the limitation in the number of parallel bits, N, raise the problem that it is impossible to increase the amount of data signals that the operation portion 161 can read and write per unit time, or to increase the transmission speed of data signals. The delays in transmission speed of data signals appear as delays in processing speed of the device 151.
FIG. 14 is a block diagram showing another conventional device which was made mainly to solve this problem. In this device 152, both of the operation portion 166 and the memory portion 167 are built in one semiconductor chip, or in a so-called single chip. Accordingly, N-bit-unit data signals are transmitted between the operation portion 166 and the memory portion 167 within a single semiconductor chip.
This suppresses the delays in data signal transmission. Further, since it is not necessary to attach N pins to a single semiconductor chip, the number, N, of signals transmitted in parallel is not limited by the restriction of the number of pins. This, too, improves the transmission speed of data signals read or written by the operation portion 166.
However, the device 152 causes another problem that the size of the storage capacity of the memory portion 167 is limited since the operation portion 166 and the memory portion 167 are built in a single semiconductor chip. Usually, a microcomputer requires semiconductor memory having a storage capacity far exceeding the semiconductor memory capacity which can be built in a single semiconductor chip.
For example, with present DRAM fabrication technology, DRAM storage capacity that can be built in a single semiconductor chip is 16 megabits (=2 megabytes). On the other hand, a CPU with ordinary performance currently requires semiconductor memory with a storage capacity of about 8 to 16 megabytes. It is well known that users of personal computers ensure required storage capacities by adding DRAMs.
In the process of advances in semiconductor technology, it is empirically known by the name of "Amdahl's Law" that the performance of CPU and the storage capacity of semiconductor memory required by the CPU are in proportion to each other. Accordingly, even if semiconductor technology advances on in future, the structure of the device 152 in which the operation portion 166 having a CPU and the memory portion 167 having DRAM are built in a single semiconductor chip will leave the problem of lack of storage capacity unsolved.